The present invention is directed to an integratable circuit arrangement for delaying pulse-shaped signals.
In pulse technology, it is often necessary to delay signals by a given time span. The distribution of clock signals in larger, fast digital circuits particularly requires compensation for signal running times on signal paths of different lengths. As known, for example, from Emmo A. Zuiderveen, Handbuch der digitalen Schaltungen, 2nd edition 1985, page 200, the transit time compensation is usually carried out with line simulations using passive components or a series-connection of a plurality of gates. Compensation, however, is difficult with the known circuit arrangements since a dimensioning of the passive components is possible only in an extremely limited range or, when gates are used, only whole-numbered multiples of the delay time of a gate are available.